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ASAHI KASEI
[AKD4665A-A]
AKD4665A-A
AK4665A Evaluation board Rev.1
GENERAL DESCRIPTION AKD4665A-A is an evaluation board for the AK4665A, 20bit CODEC with built-in Input PGA and Headphone Amplifier. The AKD4665A-A can evaluate A/D converter and D/A converter separately in addition to loopback mode (A/D D/A). AKD4665A-A also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. Ordering guide
AKD4665A-A --- Evaluation board for AK4665A (Cable for connecting with printer port of IBM-AT, compatible PC and control software are packed with this. This control software does not support Windows NT.)
FUNCTION * DIT/DIR with optical input/output * RCA connector for an external clock input * 10pin Header for serial control mode
HVDD AVDD DVDD TVDD LVC_IN GND 5V 3V Regulator
MIC-Jack AINL1/ MICIN AINR1
up-I/F 10pin Header
DSP LIN/RIN/MIN LOUT ROUT HPL HPR HP-Jack Opt In Opt Out AK4114
AK4665A
10pin Header
Figure 1. AKD4665A-A Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual.
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ASAHI KASEI
[AKD4665A-A]
Evaluation Board Manual Operation sequence
1) Set up the power supply lines. 1-1) When AVDD, DVDD, HVDD, TVDD and LVC are supplied from the regulator. (AVDD, DVDD, HVDD, TVDD and LVC_IN jack should be open.). See "Other jumper pins set up (page 5)". [REG] (red ) [HVDD] (orange) [AVDD] (orange) [DVDD] (orange) [TVDD] (blue) [LVC_IN] (blue) [VD_IN] (orenge) [AGND] (black) [DGND] (black) = 5V = open = open = open = open = open = 2.7 3.6V = 0V = 0V
: 3V is supplied to HVDD of AK4665A from regulator. : 3V is supplied to AVDD of AK4665A from regulator. : 3V is supplied to DVDD of AK4665A from regulator. : 3V is supplied to TVDD of AK4665A from regulator. : 3V is supplied to logic block of LVC from regulator. : for other logic (typ. 3V) : for analog ground : for logic ground
1-2) When AVDD, DVDD, HVDD, TVDD and LVC are not supplied from the regulator. (AVDD, DVDD, HVDD, TVDD and LVC jack should be junction.) See "Other jumper pins set up (page 5)". [REG] (red) [HVDD] (orange) [AVDD] (orange) [DVDD] (orange) [TVDD] (blue) [LVC_IN] (blue) [VD_IN] (orenge) [AGND] (black) [DGND] (black) = "REG" jack and JP2 should be open. = 2.6 3.6V : for HVDD of AK4665A (typ. 3V) = 2.6 3.6V : for AVDD of AK4665A (typ. 3V) = 2.6 3.6V : for DVDD of AK4665A (typ. 3V) = 1.6 3.6V : for TVDD of AK4665A (typ. 3V) = 1.65 5.5V : for logic block of LVC (typ. 3V) = 2.7 3.6V : for other logic (typ. 3V) = 0V : for analog ground = 0V : for logic ground
Each supply line should be distributed from the power supply unit. AVDD and DVDD each must be same voltage level, and TVDD and LVC_IN each too. 2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) 3) Power on. The AK4665A and AK4114 should be reset once bringing SW1, 2 "L" upon power-up.
Evaluation mode
In case of AK4665A evaluation using AK4114, same audio interface format should be set for both AK4665A and AK4114. About AK4665A's audio interface format, refer to datasheet of AK4665A. About AK4114's audio interface format, refer to Table 2 in this manual. Applicable Evaluation Mode (1) Evaluation of loop-back mode (Default) (2) Evaluation of using DIR of AK4114 (opt-connector) (3) Evaluation of using DIT of AK4114 (opt-connector) (4) All interface signals including master clock are fed externally.
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ASAHI KASEI
[AKD4665A-A]
(1) Evaluation of loop-back mode (Default) Nothing should be connected to PORT3. PORT1(TORX141), or X'tal mode of the AK4114 is used. When an external clock through an RCA connector (J10: MCLK) is supplied, short JP12 (XTI). JP13 (EXT) and R28 should be properly selected in order to much the output impedance of the clock generator. Then X'tal(X1) and capacitance (C35,C36) should be removed.
JP12 XTI JP19 DIR_MCLK JP14 DIR_BICK JP15 BICK_INV JP16 DIR_LRCK JP18 SDTI JP17 SDTO
THR
INV
ADC
DIR
(2) Evaluation of using DIR of AK4114 (opt-connector) PORT1(TORX141), is used. DIR generates MCLK, BICK, LRCK and SDTI from the received data through optical connector (TORX141). Used for the evaluation using CD test disk. Nothing should be connected to PORT3.
JP12 XTI JP19 DIR_MCLK JP14 DIR_BICK JP15 BICK_INV JP16 DIR_LRCK JP18 SDTI JP17 SDTO
THR
INV
ADC
DIR
(3) Evaluation of using DIT of AK4114 (opt-connector) PORT1(TORX141) and PORT2(TOTX141), or X'tal mode of the AK4114 and PORT2(TOTX141) is used. DIT generates audio bi-phase signal from received data and which is output through optical connector (TOTX141). It is possible to connect AKM's D/A converter evaluation boards on the digital-amplifier which equips DIR input. Nothing should be connected to PORT3. When an external clock through a RCA connector (J10: MCLK) is supplied, short JP12 (XTI). JP13 (EXT) and R28 should be properly selected in order to much the output impedance of the clock generator. Then X'tal(X1) and capacitance (C35,C36) should be removed.
JP12 XTI JP19 DIR_MCLK JP14 DIR_BICK
JP15 BICK_INV
JP16 DIR_LRCK
JP18 SDTI
JP17 SDTO
THR
INV
ADC
DIR
(4) All interface signals including master clock are fed externally. When all interface signals through PORT3 are supplied, the jumper pins should be set to the following.
JP12 XTI
JP19 DIR_MCLK
JP14 DIR_BICK
JP15 BICK_INV
JP16 DIR_LRCK
JP18 SDTI
JP17 SDTO
THR
INV
ADC
DIR
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ASAHI KASEI
[AKD4665A-A]
DIP Switch set up
[SW2] (MODE) : Mode Setting of AK4114 ON is "H", OFF is "L". No. 1 2 3 4 5 Name DIF0 DIF1 DIF2 CM0 OCKS1 Default OFF OFF ON OFF ON ("H") OFF ("L")
AK4114 Audio Format Setting See Table 2
Clock Operation Mode select See Table 3 Master Clock Frequency Select OFF See Table 4 Table 1. Mode Setting for AK4114
Register setting for AK4665A Audio Interface Format
Mode 0 2 4 5 DIF2 0 0 1 1 DIF1 0 1 0 0
Setting for AK4114 Audio Interface Format
DIF0 0 0 0 1
DAUX SDTO DIF1 24bit, Left justified 16bit, Right justified 0 24bit, Left justified 20bit, Right justified 0 24bit, Left justified 24bit, Left justified 1 24bit, I2S 24bit, I2S 1 Table 2. Setting for AK4114 Audio Interface Format Clock Mode Clock source SDTO PLL Mode PORT1 (TORX141) RX (Optical) X'tal Mode X1 (X'tal) or J10 (RCA) DAUX (ADC) Table 3. Clock Operation Mode select PLL Mode X'tal Mode 256fs 256fs 512fs 512fs Table 4. Master Clock Frequency Select
DIF0 0 1 0 1
Default
SW2-#4 (CM0) OFF ON
Default
SW2-#5 (OCKS1) OFF ON
Default
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ASAHI KASEI
[AKD4665A-A]
Other jumper pins set up
1. JP1 (GND) OPEN SHORT 2. JP3 (REG) OPEN
SHORT
: Analog ground and Digital ground : Separated. : Common. (The connector "DGND" can be open.) : HVDD of the AK4665A : HVDD is supplied from "HVDD " jack. : HVDD is supplied from the regulator ("HVDD" jack should be open). < Default >
3. JP3 (AVDD_SEL) : AVDD of the AK4665A OPEN : AVDD is supplied from "AVDD " jack. SHORT : AVDD is supplied from "HVDD" ("AVDD" jack should be open). < Default > 4. JP4 (DVDD_SEL) : DVDD of the AK4665A OPEN : DVDD is supplied from "DVDD " jack. < Default > SHORT : DVDD is supplied from "HVDD" ("DVDD" jack should be open). 5. JP6 (TVDD_SEL), JP7 (LVC_SEL): JP6 OPEN OPEN OPEN SHORT JP7 OPEN TVDD VD OPEN TVDD is supplied from "TVDD" jack "TVDD" jack "TVDD" jack "DVDD" "DVDD" Logic block of LVC is supplied from "LVC_IN" jack "TVDD" jack "VD_IN" jack "LVC_IN" jack "TVDD" Note "LVC_IN" jack should be open. "LVC_IN" jack should be open. "TVDD" jack should be open.
SHORT TVDD SHORT VD
"TVDD" and "LVC_IN" jack should be open. TVDD" and "LVC_IN" jack "DVDD" "VD" jack should be open. Table 5. JP6 (TVDD_SEL), JP7 (LVC_SEL) select
6. JP5 (MPWR) : Connection between MPWR pin and MICIN pin of the AK4665A OPEN : MPWR is not connected to MICIN. SHORT : MPWR is connected to MICIN. < Default >
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ASAHI KASEI
[AKD4665A-A]
The function of the toggle SW
[SW1] (DIR) : Power control of AK4114. Keep "H" during normal operation. Keep "L" when AK4114 is not used. : Power control of AK4665A. Keep "H" during normal operation.
[SW3] (PDN)
Indication for LED
[LED1] (ERF): Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114.
Serial Control
The AK4665A can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT4 (CTRL) with PC by 10 wire flat cable packed with the AKD4665A-A
Connect PC
CSN SCL/CCLK SDA/CDTI SDA/(ACK)
10 wire flat cable
10pin Connector
10pin Header AKD4665A-A
Figure 2. Connect of 10 wire flat cable
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ASAHI KASEI
[AKD4665A-A]
Analog Input / Output Circuits
(1) Input Circuits a) MIC/AINL1/AINR1 Input Circuit
J1 MIC-JACK
6 4 3
JACK RCA
JP8 MIC_SEL INT
J3 AINL1/MICIN
2 3 1
2
C25 1u +
1
AINL1
MR-552LS
R16 (open) C26 1u +
J5 AINR1
2 3 1
2
1
AINR1
MR-552LS
R17 (open)
Figure 3. MIC/AINL1/AINR1 Input Circuit (a-1) Analog signal is input to MICIN pin via J1 (MIC-JACK) connector.
JP8 MIC_SEL
RCA JACK
(a-2) Analog signal is input to MICIN pin via J3 (AINL1/MICIN) connector.
JP12 MIC_SEL
RCA JACK
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ASAHI KASEI
[AKD4665A-A]
b) LIN/RIN/MIN Input Circuit
J8 LIN/RIN/MIN
2 3 1
MR-552LS
R21 (open)
C27 0.047u
LIN RIN MIN
JP10 LIN
LIN/RIN/MIN
RIN
MIN
Figure 4. LIN/RIN/MIN Input Circuit
(2) Output Circuits a) LOUT/ROUT Output Circuit
C23 LOUT
1
+
2
R12 220
4.7u
2 3 1
J2 LOUT
R13 10k
MR-552LS
C24 ROUT
1
+
2
R14 220
4.7u
2 3 1
J4 ROUT
R15 10k
MR-552LS
Figure 5. LOUT/ROUT Output Circuit
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ASAHI KASEI
[AKD4665A-A]
b) HPL/HPR Output Circuit
J6 HPL
2 3 1
R18 16 R19 (short) HPL R20 (short) HPR JP11 HPR JP9 HPL
6 4 3
MR-552LS
J7 HP
2 3 1
J9 HPR
R22 16
MR-552LS
Figure 6. HPL/HPR Output Circuit
(b-1) HPL and HPR pins are outputted from J7 (mini jack).
JP9 HPL JP11 HPR
(b-2) HPL and HPR pins are outputted from J6 and J9.
JP9 HPL JP11 HPR
AKM assumes no responsibility for the trouble when using the above circuit examples.
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ASAHI KASEI
[AKD4665A-A]
2. Control Software Manual Set-up of evaluation board and control software
1. Set up the AKD4665A-A according to previous term. 2. Connect IBM-AT compatible PC with AKD4665A-A by 10-line type flat cable (packed with AKD4665A-A). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer "Installation Manual of Control Software Driver by AKM device control software". In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled "AKD4665A-A Evaluation Kit" into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of "AKD4665A-A.exe" to set up the control program. 5. Then please evaluate according to the follows.
Operation flow
Keep the following flow. 1. Set up the control program according to explanation above. 2. Click "Port Reset" button. 3. Click "Write default" button
Explanation of each buttons
1. [Port Reset] : 2. [Write default] : 3. [All Write] : 4. [Function1] : 5. [Function2] : 6. [Function3] : 7. [Function4] : 8. [Function5]: 9. [SAVE] : 10. [OPEN] : 11. [Write] : Set up the USB interface board (AKDUSBIF-A) when using the board. Initialize the register of the AK4665A. Write all registers that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation.
Indication of data
Input data is indicated on the register map. Red letter indicates "H" or "1" and blue one indicates "L" or "0". Blank is the part that is not defined in the datasheet.
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ASAHI KASEI
[AKD4665A-A]
Explanation of each dialog 1. [Write Dialog]: Dialog to write data by mouse operation
There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes "H" or "1". If not, "L" or "0". If you want to write the input data to the AK4665A, click [OK] button. If not, click [Cancel] button.
2. [Function1 Dialog] : Dialog to write data by keyboard operation
Address Box: Data Box: Input registers address in 2 figures of hexadecimal. Input registers data in 2 figures of hexadecimal.
If you want to write the input data to the AK4665A, click [OK] button. If not, click [Cancel] button.
3. [Function2 Dialog] : Dialog to evaluate DATT
There are dialogs corresponding to register of 05h, 0Ah, 0Bh and 0Ch. Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to the AK4665A by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to the AK4665A, click [OK] button. If not, click [Cancel] button.
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ASAHI KASEI
[AKD4665A-A]
4. [SAVE] and [OPEN]
4-1. [SAVE] All of current register setting values displayed on the main window are saved to the file. The extension of file name is "akr". (1) Click [SAVE] Button. (2) Set the file name and click [SAVE] Button. The extension of file name is "akr". 4-2. [OPEN] The register setting values saved by [SAVE] are written to the AK4665A. The file type is the same as [SAVE]. (1) Click [OPEN] Button. (2) Select the file (*.akr) and Click [OPEN] Button.
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ASAHI KASEI
[AKD4665A-A]
5. [Function3 Dialog]
The sequence of register setting can be set and executed. (1) Click [F3] Button. (2) Set the control sequence. Set the address, Data and Interval time. Set "-1" to the address of the step where the sequence should be paused. (3) Click [START] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [SAVE] and [OPEN] button on the Function3 window. The extension of file name is "aks".
Figure 7. Window of [F3]
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ASAHI KASEI
[AKD4665A-A]
6. [Function4 Dialog]
The sequence file (*.aks) saved by [Function3] can be listed up to 10 files, assigned to buttons and then executed. When [F4] button is clicked, the window as shown in Figure 8 opens.
Figure 8. [F4] window
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ASAHI KASEI
[AKD4665A-A]
6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks) saved by [Function3]. The sequence file name is displayed as shown in Figure 9. ( In case that the selected sequence file name is "DAC_Stereo_ON.aks")
Figure 9. [F4] window(2) (2) Click [START] button, then the sequence is executed.
6-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The name assign of sequence file displayed on [Function4] window can be saved to the file. The file name is "*.ak4". [OPEN] : The name assign of sequence file(*.ak4) saved by [SAVE] is loaded.
6-3. Note (1) This function doesn't support the pause function of sequence function. (2) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (3) When the sequence is changed in [Function3], the sequence file (*.aks) should be loaded again in order to reflect the change.
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ASAHI KASEI
[AKD4665A-A]
7. [Function5 Dialog]
The register setting file(*.akr) saved by [SAVE] function on main window can be listed up to 10 files, assigned to buttons and then executed. When [F5] button is clicked, the window as shown in Figure 10 opens.
Figure 10. [F5] window
7-1. [OPEN] buttons on left side and [WRITE] button (1) Click [OPEN] button and select the register setting file (*.akr). The register setting file name is displayed as shown in Figure 11. (In case that the selected file name is "DAC_Output.akr") (2) Click [WRITE] button, then the register setting is executed.
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ASAHI KASEI
[AKD4665A-A]
Figure 11. [F5] windows(2)
7-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The name assign of register setting file displayed on [Function5] window can be saved to the file. The file name is "*.ak5". [OPEN] : The name assign of register setting file(*.ak5) saved by [SAVE] is loaded.
7-3. Note (1) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (2) When the register setting is changed by [SAVE] Button on the main window, the register setting file (*.akr) should be loaded again in order to reflect the change.
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ASAHI KASEI
[AKD4665A-A]
MEASUREMENT RESULTS
[Measurement condition] * Measurement unit * MCLK * BICK * fs * Bit * Power Supply * Measurement Filter * Temperature
: Audio Precession System Two Cascade : 11.2896MHz : 64fs : 44.1kHz : 20bit : AVDD = DVDD = HVDD = TVDD = 3.0V : 10Hz 20kHz : Room
Parameter MIC-Amp: (MICIN pin ADC) THD+N (-1dBFS Output) D-Range (-60dB Output, A-weighted) S/N (A-weighted)
Result (Lch / Rch) -90.6 / -90.4 93.4 / 93.4 93.4 / 93.4
Unit dB dB dB Unit
Parameter Result (Lch / Rch) Analog Input Characteristics: (AINL1/AINR1 pins ADC IVOL), IVOL=0dB, ALC1= OFF THD+N (-1dBFS Output) -91.6 / -91.2 D-Range (-60dB Output, A-weighted) 94.5 / 94.5 S/N (A-weighted) 94.6 / 94.6 Parameter Result (Lch / Rch) Headphone-Amp: (DAC HPL/HPR pins), RL=16, HPG bit = "0", ATTL7-0=ATTR7-0 bits=0dB THD+N (0dBFS Output) -58.7 / -58.7 D-Range (-60dB Output, A-weighted) 88.4 / 88.2 S/N (A-weighted) 88.5 / 88.2 Parameter Result (Lch / Rch) Stereo Line Output: (DAC LOUT/ROUT pins), ATTL7-0 = ATTR7-0 = ATTS3-0 bits = 0dB THD+N (0dBFS Output) -84.5 / -84.1 D-Range (-60dB Output, A-weighted) 88.7 / 88.4 S/N (A-weighted) 88.8 / 88.5
dB dB dB Unit
dB dB dB Unit
dB dB dB
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[AKD4665A-A]
PLOT DATA 1.ADC (AINL1/AINR1
AKM
-60 -62 -64 -66 -68 -70 -72 -74 -76 d B F S -78 -80 -82 -84 -86 -88 -90 -92 -94 -96 -98 -100 -120 -110 -100
ADC) PLOT DATA
AKD4665 ADC(mic) THD+N vs.Input Level (fs=44.1kHz, fin=1kHz)
-90
-80
-70
-60 dBr
-50
-40
-30
-20
-10
Figure 12. THD+N vs. Input Level
AKM
-60 -62.5 -65 -67.5 -70 -72.5 -75 d B F S -77.5 -80 -82.5 -85 -87.5 -90 -92.5 -95 -97.5 -100 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
AK4665 ADC(AIN) THD+N vs. Input Frequency (fs=44.1kHz, Input=-1dB)
Figure 13. THD+N vs. Input Frequency (Input Level = -1dBFS)
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ASAHI KASEI
[AKD4665A-A]
AKM
+0 -10 -20 -30 -40 d B F S -50 -60 -70 -80 -90 -100
AK4665 ADC(AIN) Linearity (fs=44.1kHz, fin=1kHz)
-110 -110
-100
-90
-80
-70
-60 dBr
-50
-40
-30
-20
-10
+0
Figure 14. Linearity
AKM
+0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 d B F S -1.4 -1.6 -1.8 -2 -2.2 -2.4 -2.6 -2.8 -3 20
AK4665 ADC(AIN) Frequency Response (fs=44.1kHz, Input=-1dB)
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 15. Frequency Response
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ASAHI KASEI
[AKD4665A-A]
AKM
+0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50
AK4665 ADC(AINL1/AINR1) FFT (fs=44.1kHz, fin=1kHz, Input=-1dB) FFT point=16384, Avg=8
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 16. FFT Plot (Input level=-1dBFS)
AKM
+0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
AK4665 ADC(AINL1/AINR1) FFT (fs=44.1kHz, fin=1kHz, Input=-60dB) FFT point=16384, Avg=8
Figure 17. FFT Plot (Input level=-60dBFS)
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ASAHI KASEI
[AKD4665A-A]
AKM
+0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50
AK4665 ADC(AINL1/AINR1) FFT (fs=44.1kHz, Input=no signal) FFT point=16384, Avg=8
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 18. FFT Plot (no signal input)
Figure 19. Crosstalk
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ASAHI KASEI
[AKD4665A-A]
2. DAC (DAC
AKM
-70
LOUT/ROUT) PLOT DATA
AK4665 DAC(LINEOUT) THD+N vs.Input Level (fs=44.1kHz, input=0dB)
-72
-74
-76
-78 d B r A -82
-80
-84
-86
-88
-90 -120
-110
-100
-90
-80
-70
-60 dBFS
-50
-40
-30
-20
-10
+0
Figure 20. THD+N vs. Input Level
AKM
-70
AK4665 DAC(LINEOUT) THD+N vs.Input Frequency(fs=44.1kHz, input=0dB)
-72
-74
-76
-78 d B r A -82
-80
-84
-86
-88
-90 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 21. THD+N vs. Input Frequency (Input Level = 0dBFS)
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ASAHI KASEI
[AKD4665A-A]
AKM
+0 -10 -20 -30 -40 d B r A -50 -60 -70 -80 -90 -100
AK4665 DAC(LINEOUT) Linearity (fs=44.1kHz, input=0dB)
-110 -110
-100
-90
-80
-70
-60 dBFS
-50
-40
-30
-20
-10
+0
Figure 22. Linearity
AKM
+0.5 +0.4 +0.3 +0.2 +0.1 +0 -0.1 d B r A -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1 2k 4k 6k 8k 10k Hz 12k 14k 16k 18k 20k -0.2 -0.3
AKD4665 DAC(LINEOUT) Frequency Response (fs=44.1kHz, Input=0dB)
Figure 23. Frequency Response
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ASAHI KASEI
[AKD4665A-A]
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50
AK4665 DAC(LINEOUT) FFT (fs=44.1kHz, fin=1kHz, Input=0dB) FFT point=16384, Avg=8
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 24. FFT Plot (Input level=0dBFS)
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
AK4665 DAC(LINEOUT) FFT (fs=44.1kHz, fin=1kHz, Input=-60dB) FFT point=16384, Avg=8
Figure 25. FFT Plot (Input level=-60dBFS)
- 25 -
2006/05
ASAHI KASEI
[AKD4665A-A]
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50
AK4665 DAC(LINEOUT) FFT (fs=44.1kHz, Input=no data) FFT point=16384, Avg=8
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 26. FFT Plot (no data input)
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k Hz 2k 5k 10k 20k 50k 100k
AK4665 DAC(LINEOUT) Out band noise (fs=44.1kHz, Input=no data) FFT point = 16384, Avg = 8
Figure 27. Out band noise (no data input)
- 26 -
2006/05
ASAHI KASEI
[AKD4665A-A]
Figure 28. Crosstalk
- 27 -
2006/05
ASAHI KASEI
[AKD4665A-A]
3. DAC (DAC
AKM
-50 -52 -54 -56 -58 -60 -62 -64 -66 d B r A -68 -70 -72 -74 -76 -78 -80 -82 -84 -86 -88 -90 -120 -110
HPL/HPR) PLOT DATA
AKD4665 DAC(HP) THD+N vs.Input Level (fs=44.1kHz, fin=1kHz)
-100
-90
-80
-70
-60 dBFS
-50
-40
-30
-20
-10
+0
Figure 29. THD+N vs. Input Level
AKM
-30 -35 -40 -45 -50 -55 d B r A -60 -65 -70 -75 -80 -85 -90 -95 -100 20
AK4665 DAC(HP) Input Frequency (fs=44.1kHz, Input=0dB)
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 30. THD+N vs. Input Frequency (Input Level = 0dBFS)
- 28 -
2006/05
ASAHI KASEI
[AKD4665A-A]
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50
AK4665 DAC(HP) FFT (fs=44.1kHz, fin=1kHz, Input=0dB) FFT point=16384, Avg=8
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 31. FFT Plot (Input level=0dBFS)
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
AK4665 DAC(HP) FFT (fs=44.1kHz, fin=1kHz, Input=0dB) FFT point=16384, Avg=8
Figure 32. FFT Plot (Input level=-60.0dBFS)
- 29 -
2006/05
ASAHI KASEI
[AKD4665A-A]
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100
AK4665 DAC(HP) FFT (fs=44.1kHz, Input=no data) FFT point=16384, Avg=8
200
500 Hz
1k
2k
5k
10k
20k
Figure 33. FFT Plot (no data input)
Figure 34. Crosstalk
- 30 -
2006/05
ASAHI KASEI
[AKD4665A-A]
Revision History
Date (YY/MM/DD) 05/12/19 06/05/17 Manual Revision KM082200 KM082201 Board Revision 0 1 Reason First Edition Circuit change Contents
A 2 resistor was inserted at HVDD line in series.
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
- 31 -
2006/05
A
B
C
D
E
REG
T1 TA48M03F
IN GND OUT 1
JP1 GND CCLK/SCL CSN/CAD0 4665_AVDD CDTI/SDA
REG1 T45_R
1
HVDD1 T45_O
1
AVDD1 T45_O
1
DVDD1 T45_O
1
TVDD1 T45_B
1
AGND1 T45_BK
1
E
DGND
AGND
PDN
C2 0.1u
C3 0.1u
C1 + 47u
E
2
REG
HVDD
AVDD
DVDD
TVDD
HVDD L1
1 1 2
JP2 REG
CN1 32pin_4 R100 2 4665_HVDD
LVC_IN1 VD_IN1
32 31 30 29 28 27 26 25
DGND1 T45_BK
1
T45_B
1
T45_O
1
C4 47u
+
2
(short)
1
C5 4.7u
2
C6 2.2u
1 2
+
LVC_IN VD_IN
AVDD
D
L2
1 1 2
31
28
30
32
29
C10 47u
VCOM
R6 CN3 DVDD L3
1 1 2
51
1 LRCK
AVDD
AVSS
CSN
CCLK
PDN
VREF
CDTI
+
2
(short)
27
26
25
JP3 AVDD_SEL 4665_AVDD
R1 10 U1
R2 51
R3 51
R4 51
R5 51
C7 0.1u
+
C8 0.1u
D
C9 0.1u
MICIN
24
JP4 DVDD_SEL
LRCK MCLK BICK SDTI
1 2 3
R8
51
2 MCLK MPWR 23
C11 0.22u R9
3 BICK AINL1 22
JP5 MPWR
CN2
24
INT
C12 47u
+
2
(short)
R10 51
2.2k
23 22
R7
4 5 6 7 8 1
51
4 SDTI AINR1 21
AINL1 AINR1 LIN RIN MIN LOUT
C
21
TVDD L4
1 1 2
JP6 TVDD_SEL
SDTO
R11 51
5 SDTO
C
4665A
LIN
20
20 19 18
6
C13 47u
+
2
(short)
TVDD
RIN
19
C14 10u
+
2
C15 0.1u
7
32pin_1
C16 0.1u
8
DVSS
MIN
18 17
DVDD HVDD ROUT HVSS NVSS HPR HPL
LOUT
17
32pin_3
9
10
CN
CP
11
12
13
14
15
B
16
B
LVC_IN L5
1 1 2
JP7 TVDD LVC_SEL LVC VD
C17 2.2u
1
C18 C19 0.1u 2.2u
2
C21 47u
+
2
(short)
C20 10u
10
11
12
13
14
15
32pin_2 VD_IN 4665_HVDD
1 1
A
2
VD
ROUT
HPR
HPL
L6 C22 47u +
2
16
CN4
9
+
(short)
A
Title Size Document Number
AKD4665A-A
AK4665A
Sheet
E
Rev
A3
Date:
A B C D
1 1
of
Wednesday, May 17, 2006
4
A
B
C
D
E
J1 MIC-JACK
6 4 3
E
INT RCA
LOUT
1
+
JACK
JP8 MIC_SEL
C23
2
R12 220
2 3 1
J2 LOUT
E
4.7u
R13 10k
MR-552LS
C24 ROUT J3 AINL1/MICIN
2 3 1 2 1
+
R14 220
2 2 3 1
J4 ROUT
C25 1u
1
4.7u AINL1
R15 10k
MR-552LS
+ R16 (open)
MR-552LS
D
D
J5 AINR1
2 3 1 2
C26 1u
1
AINR1
2 3 1
J6 HPL
+ R17 (open)
MR-552LS
R18 16 R19 (short) HPL R20 (short) JP9 HPL
MR-552LS
J7 HP
6 4 3
C
C
J8 LIN/RIN/MIN
2 3 1
HPR LIN 2 RIN 4 MIN 6 JP10
1 3 5
LIN
MR-552LS
R21 (open)
C27 0.047u
JP11 HPR J9 HPR
2 3 1
LIN/RIN/MIN
RIN
MIN R22 16
MR-552LS
B
B
A
A
Title Size Document Number
AKD4665A-A
ANALOG
Sheet
E
Rev
A3
Date:
A B C D
1 2
of
Wednesday, May 17, 2006
4
A
B
C
D
E
C28 C29 0.1u 0.1u VD
1
VD L7 (short)
U2A 74HC14_1 C31 10u
2 1 2
E
VD
14
74HC14_1 U2B VD
1 4 7 14 3
R23 10k
K
PORT1
VCC GND OUT 3 2 1
C30 0.1u R24 470
3
C33 0.1u
C32 0.1u
2
1
TORX141
VD
7
L
A
D1 HSU119
E
2
H SW1 DIR
+
C34 0.47u
R25 18k
45
41
39
47
43
48
46
44
D
DIF0 DIF1 DIF2 CM0 OCKS1
SW2
1 2 3 4 5 10 9 8 7 6
U4
42
40
38
37
VCOM
AVSS
TEST1
AVDD
NC
RX3
RX2
RX1
NC
RX0
INT1
VD U3A
2
R
D
R26 1k
K
LED1 ERF
A
1
IPS0
INT0
36
1 7
14
VD
MODE
2 NC OCKS0 35
74HC04
RP1
6 5 4 3 2 1 3 DIF0 OCKS1 34
OCKS1
CM0 OCKS1
4
TEST2
CM1
33
47k
5 DIF1 CM0 32
CM0
C
C
6
NC
1
7
DIF2
AK4114
PDN
31
C35 5p
XTI 30
X1 11.2896MHz
IPS1 XTO 2 8 29
C36 5p
JP12 XTI
R27 51
2 3 1
MCLK J10
9
P/SN
DAUX
28
DAUX
JP13 EXT
MR-552LS
10
XTL0
MCKO2
27
11
B
XTL1
BICK
26
R28 51 DIR_BICK
B
12
VIN MCKO1 DVDD COUT UOUT BOUT VOUT DVSS DVSS TVDD LRCK TX0 TX1
SDTO
25
DIR_SDTI
13
14
15
16
17
18
19
20
21
22
23
C37 0.1u +
C38 0.1u +
24
DIR_LRCK
1
2
1
2
DIR_MCLK
C39 10u VD PORT2
A
C40 10u VD
A
IN VCC GND
3 2 1
VD C41 0.1u
Title Size Document Number
TOTX141
AKD4665A-A
DIR/DIT
Sheet
E
Rev
A3
Date:
A B C D
1 3
of
Wednesday, May 17, 2006
4
A
B
C
D
E
LVC
1 2 3 4 5 6 7 8 9
R29 1k VD LVC
14
U5A
1
VD
K
E
14
14
A
D2 HSU119
R30 10k
5
VD
U2C 74HC14_1 VD
U2D 74HC14_1
RP2 R-PACK8R
DAUX
2 7
SDTO
E
74LVC07 VD
C46 0.1u
14
6 7
9 7
8
PDN1 SDTI
2
U6A
1
L
3 1
H SW3 PDN
2
SDTI1
74LVC07 U6B
3
BICK
4 7
14
C42 0.1u
VD
7
BICK1
74LVC07 U6C
5
VD MCLK
D
6 7
14
MCLK1
D
VD
14
U2E 74HC14_1 INV JP15
10 1 2 3
74LVC07 U6D
9
VD LRCK
8 7 14
JP14 DIR_BICK DIR_BICK
11
BICK1
LRCK1
74LVC07 U6E
11
7
THR BICK_INV CCLK/SCL JP16 DIR_LRCK CSN/CAD0 JP19
C
10 7
14
CCLK1/SCL
74LVC07 U6F
13
12 7
14
DIR_LRCK
LRCK1
CSN1/CAD0
DIR_MCLK DIR_MCLK
MCLK BICK LRCK SDTI VD
PORT3
1 2 3 4 5 10 9 8 7 6
GND GND NC NC SDTO
74LVC07 U8A
1
C
VD JP17 PDN SDTO
2 7 14
PDN1
MCLK1
DSP
74LVC07
VD R31 10k JP18 1 ADC SDTI1
2 3
C44 0.1u
VD LVC
14
C45
4
DAUX DIR_SDTI
U3B 74HC04 0.1u U5C 74LVC07
5 7 6 14
C47 0.1u
VD
3 7
DIR
SDTI
14
U3C 74HC04
6
5
14 6
B
U8C
B
CCLK1/SCL VD R32 R33 R34 10k 10k 10k R36 R35 R37 470 470 470
14
VD U8B
9 3 4 7
7
14
14
U3D
8 9
8 7
9 7
14 8 14 10 7 14 12 7
U5D
U8D 74LVC07
14
14
LVC uP-I/F
14
13
12 13 7
VD
R39
1k
4
74HC14_1
U3F
12 13
14
1 2 3 4 5
10 9 8 7 6
U2F
14
CSN SCL/CCLK SDA/CDTI SDA(ACK)
C43
11
U3E
10 11
14
PORT4 A1-10PA-2.54DSA
74LVC07
VD
7
CDTI/SDA
74HC04
74LVC07 U5E U8E
10 7 11
R38
51
0.1u
74HC04
74LVC07 U5F
74LVC07 U8F
12 13
7
U5B
3
74HC04
74LVC07
7
74LVC07
A
7
7
CSN1/CAD0
5
74LVC07
74LVC07
Title Size Document Number
A
7
AKD4665A-A
Interface
Sheet
E
Rev
A3
Date:
A B C D
1 4
of
Wednesday, May 17, 2006
4

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